This paper describes an electrical and physical failure analysis methodology leading to a unique defect called residual EG oxide (shortened to REGO); which manifested in 14nm SOI high performance FinFET technology. Theoretically a REGO defect can be present anywhere and on any multiple Fin transistor, or any type of device (low Vt, Regular Vt or High Vt). Because of the quantum nature of the FinFET and REGO occurrence being primarily limited to single Fins, this defect does not impact large transistors with multiple FINs; moreover, REGO was found to only impact 3 Fin or less transistors. Since REGO can be present on any multi-FIN transistor the potential does exist for the defect to escape test screening. Subsequently a reliability BTI (Bias Temperature Instability) stress experiment by nanoprobing at contact level was designed to assess REGO’s potential reliability impact. The BTI stress results indicate that the REGO defect would not result in any additional reliability or performance degradation beyond model expectations.

This content is only available as a PDF.
You do not currently have access to this content.