Abstract

In this paper, the stacking fault defects in FinFETs are described as the root cause of the PLL failure. Failure analysis approaches such as photon emission microscopy and nano probing were applied to pinpoint the exact stacking fault location in even transistor level and High resolution TEM confirmed the stacking fault defects in the Fin which was isolated by nano probing. RX local density was confirmed as the key factor in stacking fault generation by TCAD simulation. RX new mask with dummy addition was made to mitigate stress and was confirmed to be effective to reduce the compressive strain at the channel in FinFETs by Geometric Phase Analysis (GPA) which provided sufficiently practical local strain measurement data. The GPA techniques demonstrated here are informative for process improvement and failure analysis in FinFET devices.

Keywords – Stacking Fault, Geometric Phase Analysis

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