In this paper the authors will discuss an application of Single Shot Logic (SSL) patterns used for further localizing IDDQ failures using ATPG constraints and targeted faults. This new method provides the analyst a possibility of performing circuit analysis using IDDQ measurement results as a pass/fail criterion rather than logic mismatches. Once a defective area was partially isolated through fault localization, SSL patterns were created to control individual internal node logic states in a deterministic way. IDDQ was measured at each SSL iteration where schematic analysis can further isolate the failure to a specific location. Two case studies will be discussed to show how this technique was used on actual failing units, with detailed explanation of the steps performed that led to a more precise determination of the fault location in the suspect cell.