FIB/SEM and TEM are standard characterization techniques for evaluation of process modification of microelectronics samples. In this paper, artefacts from these techniques are studied. The sample preparation methods are optimized to avoid damages. Seal-ring structures are chosen as an example in this study to show artefacts and difficulties in SEM and TEM observations. Two cases of artefacts are considered: one with TEM sample preparation followed by TEM imaging, and the other one with SEM observations after FIB cross-sectioning. In the first case, electronic chips that failed during stress tests are investigated, while in the second case a part has been dismissed during robustness qualification test. In the former, thickness of TEM lamellae has been evidenced as a key factor for delamination between layers under beam, whereas in the latter, it was observed that the electron beam lead to a shrink of oxide layers, which induced the break of underlying contacts.