We present a case study where an APG (Algorithmic Pattern Generator) based pattern from a memory tester is being converted to run on a logic FA tester. Due to the regular structure of memory patterns, the APG patterns are written in a high-level based language and converted on a real-time basis to be executed on the hardware. A logic analyzer is used to capture the test pattern that is seen by the Device Under Test (DUT). The captured test pattern is then converted to the Standard Test Interface Language (STIL) based pattern format with the help of a scripting language. An existing test program is modified to include the Timing, Levels, Specs and the pin configuration to adapt to the DUT. The failing condition for FA could be exactly reproduced after running the pattern on the FA tester and can be made as a generic solution for similar exercises.

This content is only available as a PDF.
You do not currently have access to this content.