Failure Analysis of SRAM DQ Fault Using BIST Pattern

SRAM failure analysis (FA) provides significant value to process improvement and yield enhancement. This paper introduces an innovative method to analyze the SRAM peripheral, particularly its input/output (DQ) failures, which is not easy to isolate the fault location. In this paper, SRAM Built-In Self-Test (BIST) logic is used to generate the vectors to toggle only DQ of SRAM and an optical fault isolation technique applies to isolate the fault location. Experimental results show that the proposed method is very effective to isolate timing fault and hard defect of SRAM DQ failures.