This electrical fault isolation based on Xilinx 28nm all programmable device in a Distribution RAM (LUTRAM) functional block. The Look-Up-Table (LUT) was the major component to achieve the programmable chip versus the ASIC chip. In the device architecture, one 6-inputs-LUT (LUT6) memory can be configured as a 64bits distribution RAM (LUTRAM64) or two 32bits distribution RAMs (LUTRAM32). The Vivado design and debug tool brought up two powerful Intellectual Property (IP) Cores: Virtual Input/Output (VIO) and Integrated Logic Analyzer (ILA). This debug tool used Block RAM (BRAM) and fabric routing resources to store the full test results and achieved package level probe-less.  It can probe LUTRAM block input, output and Build-In Self-Test (BIST) interconnects. However the limitation was that the inner primitive functional block LUTRAM like memory cells, decoders, mode switchers, write/read controllers and so on were not able to probe. In this case study, the defect was not conventional failure inside the LUTRAM memory cell or stuck on Address/Data_in inputs. Moreover the test behavior with LUTRAM64 mode had conflicting results, which made the fault isolation even more challenge to narrow down from complex LUTRAM control circuitry to transistor level. Therefore different pattern test methodologies, pattern commonality analysis and hypothesis verification were wisely compiled together. In the end, the defect was successfully localized at the fault Isolation circuitry. It was fully matching with the failing mode and proving the fault isolation was correct. The physical defect analysis shown multiple layers metal fusing. The defect shorted the internal control output with the GND signal, which forced LUTRAM to setup as an invalid mode.