In the vicinity of a through silicon via (TSV) used in 3D chip integration, the effect of dedicated strain engineering to enhance the carrier mobility in the channel of metal oxide semiconductor field effect transistors (MOSFETs) is superposed by a strain caused by cooling down from high process temperatures to room temperature. This additional strain influences the transistor characteristics, and consequently the product performance. The measurement of strain with high spatial resolution requires TEM-based methods. In this paper, convergent beam electron diffraction (CBED) is used for strain measurement. The strain state is significantly changed during the preparation of the TEM lamellae. The exact sample geometry and accurate materials parameters were used in FE modelling and strain simulation based on a physical model. The strain in silicon at several distances from the TSV were determined experimentally using TEM-CBED and compared with numerical simulations. High-quality sample preparation is crucial for reliable and reproducible TEM-based strain data, i.e., it is a necessary precondition for strain release correction based on FE modelling and simulation.

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