Abstract

A BEOL compatible Metal-Insulator-Metal capacitor (MIMCAP) was successfully developed for GlobalFoundries 14nm technology node, and subsequently introduced on customer designs as decoupling capacitors. The lead production silicon wafers with MIMCAP showed good functionality at wafer SORT functional test. However, upon testing more wafers, it became evident that the wafer center was impacted by abnormal scan logic fallout. The observed yield loss did not correlate with the MIMCAP scribe line Health Of Line (HOL) structures and the failure root cause could not be directly pin pointed to the MIMCAP process integration. Product scan diagnostic was performed and several systematic failing logical nets were identified. Subsequent failure analysis showed open via contacts in the MIMCAP vicinity. A detailed layout analysis of the FA confirmed weak-points and repeating logic nets allowed identifying a chip design topography issue resulting in a narrower process window compared to the scribe line MIMCAP HOL structure. Thanks to this knowledge the MIMCAP process was further optimized and the wafer center fallout was fully recovered in volume production.

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