Lock-in thermography (LIT) phase data is used to generate phase shift versus applied lock-in frequency plots to estimate defect depth in semiconductor packages. Typically, samples need to be tested for an extended time to ensure data consistency. Furthermore, determining the specific point on the thermal emission site to collect data from can be challenging, especially if it is large and dispersive. This paper describes how the use of new computational algorithms along with streamlined and automated workflows, such as self-adjusting thermal emission site positioning and phase measurement auto-stop, can result in improvements to data repeatability and accuracy as well as faster time to results. The new software is applied to generate the empirical phase shift versus applied lock-in frequency plot using 2.5D IC devices with known defect location. Subsequently, experimental phase shift data from reject 2.5D IC devices with unknown defect locations are obtained and compared against the empirical phase shift plot. The defect Z-depth of these devices are determined by comparing where the experimental phase shift data points lies with respect to empirical phase shift plot and validated with physical failure analysis (PFA).