Reduced noise immunity due to dimensional shrinkage, lower operational voltages and increasing densities results in increased soft or random failures. In practice, noises are generated by complex operation of device. In Dynamic Random Access Memory (DRAM), failures by noise are regarded as either decrease in charge at cell capacitor or increase in systematic interferences. Simple equivalent circuit of One Transistor One Capacitor (1T1C) DRAM and theoretical approach in time-domain are provided for quantitative noise analysis related to sense amplifier circuitries. Results show that local voltage fluctuation reduces sensing margin to judge data-0 or data-1. This phenomenon is easily observed at 1T1C with high resistance because response of voltage generator is comparatively slow.