Case Study of ESD-induced Pin Leakage Failure Solved Using Novel Powered TIVA Technique

A case study is presented of a core CPU product where FA/FI debug is performed for an ESD-related pin leakage issue on an IO family to root cause and qualify the product. A Powered TIVA technique is used to localize the damage to the termination resistor circuitry of the affected IO block when the pin is tristated using a device tester. Failure characterization shows a gate to drain short on the transistor, with nanoprobing confirming a solid short on gate to drain and TEM finding a short at the location indicated by the TIVA hits.