Mechanical stress is a critical parameter in the design and manufacture of devices in very large scale integrated (VLSI) circuits. Whether intentionally introduced or parasitic, mechanical stress in nanoscale silicon technologies can alter carrier mobility as by as much as 25%, which can significantly affect device performance. Currently stress metrology for in-line production is conducted only at a wafer monitor level. For design purposes, the stress state in active device regions is usually inferred from electrical data. In this paper an instrument which we have developed is described for measuring mechanical stress in nanoscale silicon devices with high spatial resolution using scanning surface photovoltage microscopy (SSPVM). Other existing techniques are generally not suitable for making such measurements on production silicon nano-device structures in situ.