In modern electronic designs, more and more memories are embedded in a single chip. With the latest technologies, defects due to the manufacturing process are more prone to occur in the periphery of the memory. Obtaining a fast and accurate localization of such defects has become much more difficult with traditional diagnosis approaches that do not allow a fast-enough yield learning and improvement. This paper describes a new and automated diagnosis flow for SRAMs to determine the localization of any given defect and thus, to precisely guide the Failure Analysis phase. Based on the electrical and topological fault signatures obtained through traditional methods, each potential fault on the identified active nets is automatically simulated to retrieve the best defect candidates. This paper also presents preliminary results on a representative case study.

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