This paper proposes a compact and robust topology descriptor for the automated identification of logic gates during the reverse engineering of full integrated circuits (ICs). This gate signature proves to be very insensitive to technology scaling, device sizing or layout extraction accuracy. Based on this new descriptor, an automated gate identification tool named Gate-X is implemented on top of commercial IC design tools. The speed tests for a practical 100k-gate digital IC example show that the complete sea of gates can be identified in a few hours.

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