This work outlines a case study of charge-induced damage to SOI wafers that caused gate leakage in discrete transistors and static leakage in packaged integrated circuits (ICs). The consequential yield fallout occurred primarily at wafer center. Electrical, optical, and laser-based failure analysis techniques were used to characterize the damage and determine root cause of electrical failure. The failure mechanism was localized to a rinse step during chemical mechanical planarization (CMP). Furthermore, both current-voltage (IV) sweeps and characteristic spatial patterns generated by thermally-induced voltage alteration (TIVA) were used to capture the trends on both packaged ICs and SOI wafers for this type of charge-induced damage; this led to quick identification of another source of charge-induced damage that affected the post-fab yield.