In this paper, the effects of an open defect resulting in floating gate on combinational logic gate structures are studied. From this study, a novel method is derived to predict and narrow down the potential open defect location from a long failure path that is driving multiple branches of input nodes, into a much smaller segment without EBAC analysis. This method is applied with great success to localize open defects on actual low yield cases from advanced technology nodes with significant reduction in FA cycle time.

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