Abstract

Wet Chemical Deprocessing is one of the techniques in exposing embedded structures in an integrated circuit (IC). Layers of the die from the passivation to silicon substrate can be selectively etched using this technique. From series of evaluations conducted, it was discovered that there are silicon damage sites that are induced during wet chemical deprocessing. Their physical attributes are almost identical to the attributes of electro-static discharge (ESD) defects. It only differs in the locations where they occur. ESD defects are expected near the edges of the transistors’ gate channel where high electric fields are present while deprocessing artifacts are observed at the center of the gate channel. Deprocessing artifacts are represented by mechanically induced damage sites in the silicon substrate. These mechanical damage sites manifest in the form of silicon pits, voids, slits and fractures as a result of tensional or shearing stresses in the silicon substrate when the polysilicons separate from the silicon substrate. If deprocessing artifacts are not well understood by the analysts then these can be mistakenly reported as ESD or fabrication defects.

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