The open bit line architecture scheme is an effective method to achieve higher density memory devices. With the scaling of DRAM, we have adopted a bit line sense amplifier (BLSA) design using a shared local power line for reducing the circuit layout dimensions. As a result of this new design, the write time of the memory cell was sometimes degraded because of an increase in initial sensing noise. This paper gives a detailed analysis of the problem caused by the initial sensing noise by examination of the behaviour of the opposite data portion of the cell array matrix when the word line is not activated. Finally, we propose a design improvement to reduce the magnitude of noise peaks and the results of this improvement when implemented in the test vehicle.

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