In order to educate students in a practical way, a test object for a lab course is created: shorts and opens in an electrical model of physical defects are injected to a net list of a 4-bit arithmetic logic unit and are implemented in a Xilinx CPLD 9572XL. The fails are electrically controllable and observable in verification and electrical hardware test. By using a Test Access Port (TAP), the fails are analyzed in terms of their root cause. The arithmetic logic unit is used as a key component for lab exercises that complement the test part of an Integrated Circuit System Design and Test course in the master program Electrical Engineering and Information Technology at the University of Applied Sciences in Rosenheim. The labs include an introduction to a HILEVEL Griffin III test system, creation of pin and test setup, the import of vector files from verification test benches, control of a scan test engine and analysis of scan test data.

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