During the early stage of process development, the major activities are yield ramp up with DFT test such as Memory BIST and SCAN test. There are plenty of commercial and inhouse diagnostics tools for DFT so in case of failure FA procedures are rather simple and standardized: run EDA tool, get fail location, perform pFA then feedback to process engineering. However in the case of marginal failure FA procedures are generally more complicated. FA engineer should consider many different scenarios to find the root cause. The marginal voltage fail is caused by many different reasons. The analysis of marginal fail is of course very important to screen out healthy devices and detect any problem of process technology or design methodology. In this paper, the authors deal with three marginal voltage fail case studies: scan chain fail, digital function fail and analog function fail. Throughout these case studies, LADA was successfully used to define the fault location. The reason of device alteration was well explained with further study. It is obvious that LADA is a very effective way to analyze marginal failures in cases where the FA engineer doesn’t have much design information because the results are very intuitive and clear. There is little doubt of LADA results accuracy because LADA is utilizing the tester to make an accurate Pass/Fail decision. LADA results are direct indication of device sensitivity to parametric changes, in our case voltage margin.

This content is only available as a PDF.
You do not currently have access to this content.