Leakage current from bit line to SNC (Storage Node Contact) is one of the most critical issues in DRAM operation. Such failure becomes more difficult to visualize as the device shrinks. In this study, bit line to SNC leakage fail was analyzed using nano-probing tool in 2xnm DRAM technology.

DRAM, failure analysis, leakage current, nanoprobing, semiconductor devices
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Copyright © 2014 ASM International. All rights reserved.
2014
ASM International
Topics
Semiconductor wafer fabrication
Issue Section:
Nanoprobing
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