Challenges of Small Defect Analysis in Large Analog Power FET Arrays

The proverbial needle in the haystack – locating a minute process defect or subtle ESD strike in a large sea of analog output power FETs can be just that. The premise of this paper is to discuss failure analysis techniques used to identify these elusive “needles”, specifically in large array power FET structures. Two case studies will be explored in detail – both of which are 250nm technology devices.