Parallel lapping (often called delayering) is a commonly used process in failure analysis of integrated circuits. However, parallel lapping commonly gives rise to the issue of weak sample preparation method especially on specimen mounting. The traditional specimen mounting technique was done by mounted a single die to polishing fixture using drop of super glue. Using conventional methods, problems such as losing the die during polishing, serious edge rounding are often encountered. Further, loading the whole polishing fixture into Scanning Electron Microscopy machine for SEM imaging or Passive Voltage Contrast (PVC) fault localization can be complicated due to the size of polishing fixture. Therefore, an alternative, relatively fast and simple method to overcome the above mentioned obstacles is proposed.

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