With the 14nm technology node becoming a reality at today's state-of-the-art semiconductor manufacturing plants and the 10nm node actively being planned for, device structures have shrunk well beyond the minimum conventional transmission electron microscope (TEM) sample thickness: 50-100nm. This paper addresses the challenges in TEM sample preparation of sub 22nm three-dimensional test structures. As semiconductor device technology continues to shrink and become more complicated with the addition of three-dimensional device integration, unique sample preparation challenges will continue to arise. This opens the door to novel solutions for these problems like the one presented in this paper: an issue that arose where TEM projection effects interfered with proper characterization of a finFET test structure.

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