Memory Scramble Verification by Frontside and Backside FIB Modification

Backside FIB circuit edit is an effective way to modify circuit on flip chip or stacked chips. Directly damaging memory cell through bulk silicon by FIB can be used to locate bit address to verify that the scramble test program coordinates correspond to the physical cell location. This paper presents the application of FIB for chip editing, discusses the limitation of the FIB approach and reports the scramble test experiments about the front-side and backside FIB technique to correct scramble testing data.