The physical analysis of sub-100nm device technologies in many cases requires the total or partial removal of the multiple layers of metallization that route electrical signals and power through the device. This paper presents a simple and quick polishing technique that will remove the entire metallization stack above metal 1 for a 55nm technology device, which results in significantly reducing the time needed to reach the transistor level of the device and also greatly improving uniform planarity across the device. This method is intended for those cases in which gaining access to the transistor layer is required for electrical characterization and physical analysis. The improved speed of this polishing technique to reach the transistor layer has greatly reduced cycle time. The results for the polishing method have been relatively reliable with over a 95% success rate.

This content is only available as a PDF.
You do not currently have access to this content.