We demonstrate an effective way of reducing off-leakage current in sub-wordline driver pMOSFETs with lightly-doped source/drain, where gate-induced drain leakage current is much relaxed, compared with those of asymmetric source/drain. In mobile DRAM, one of key parameters is to achieve an extremely low level of standby current in power consumption. What has been found is that an increase of offleakage current in the pMOSFET is related closely to a contact-formation process, in particular, TiSi2 in p+/n junction. When a direct contact becomes close to a source/drain region, a titanium atom in TiSi2 tends not only to diffuse into a depletion region of p+/n junction but to play a critical role in leakage current. Maximizing a distance between p+ gate and its direct contact should be emphasized in order to control offleakage current in such a pMOSFET.