In this paper, we investigate that Gate-Induced Drain Leakage (GIDL)-weak cells can be screened effectively by modulation of cell-plate voltage (VPlate) during retention time in dynamic random access memory (DRAM) with Negative Wordline bias scheme (NWL). Boosting storage-node voltage (VSP) by increase of VPlate is the root cause of generating additional GIDL fail bits.

DRAM devices, leakage current, negative word-line bias scheme, root cause analysis
This content is only available as a PDF.
Copyright © 2013 ASM International. All rights reserved.
2013
ASM International
Topics
Semiconductor wafer fabrication Root cause analysis
Issue Section:
Poster Session
You do not currently have access to this content.