For 22nm and below technologies which involve as many as fifteen back end of the line (BEOL) metallization levels, these leading edge technology nodes pose real challenges in defect localization and root cause analysis. Due to scaling, the reduction in copper land cross section area is accompanied by increased current density and electromigration failure rates. Time to Dielectric Defect Breakdown (TDDB) shows an increase in fallout with successive technology node from 32nm and below. Similarly, the reduced dielectric thickness increases the electric field stress prompting the necessity for porous, ultra low k dielectric (ULK) films. Defect localization is difficult due to the complexity of these multiple metal layers along with the presence of the porous, low k dielectric films which exhibit shrinkage or void formation when exposed to an e-beam/FIB ion beam > 1keV. Due to the porosity of these ULK dielectric films, they are especially susceptible to gallium ion implantation. It has been reported elsewhere that suppressing copper diffusion at the copper land/cap interface can be achieved by depositing a thin layer of CoWP and doping the copper seed layer with manganese [15, 16, 17]. However, a method for analytically confirming that these approaches for suppressing the copper diffusion do not affect TDDB performance/electromigration behavior must be demonstrated.

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