Gate Leakage Characterization and Fail Mode Analysis on 20 nm Technology Parametric Test Structures

Test structure characterization plays a predominant role throughout the entire development cycle of a product. They are used to understand the process windows and also help to monitor the health of line (HOL). One of the key principles in successfully monitoring the HOL is to establish passing and failing electrical criteria to various test structures. This paper shows electrical and physical characterization of one such test structure. Further, a novel way of establishing electrical signatures to specific defect fail mode finger prints for early identification and monitoring of process-related defects is proposed.