The trend to higher integration of electronic devices to include more functions into ever-smaller devices, such as mobile phones or tablet computers, drives the development of novel packaging technologies for semiconductor chips. One of the approaches to reduce packaging size and power consumption is to stack multiple silicon chips on top of each other. An alternative approach is the utilization of through-silicon vias (TSV) to connect multiple chips to each other. This paper provides a set of sample preparation and analysis techniques for the comprehensive analysis of TSVs in support of technology development and qualification. The toolset ranges from simple cross-section imaging of cleaved samples to the evaluation of wafer planarity at the end of the TSV process flow and to the more specific analysis of the stress field around TSVs. The results provide valuable insights for designers, integration engineers, and process engineers.

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