Failure analysis for Static Random Access Memory (SRAM) is the major activity in any microelectronic failure analysis lab. Originating from SRAM array structure, SRAM failure can be simple as single bit, paired bit or quad bit failures, whose defect is located at the failure location, or complicated as logic type failure involving WL or BL patterns or entire blocks, whose defect is often not at the failure location. For such SRAM logic type failures, failure analysis is more challenging and detailed fault isolation is necessary prior to physical failure analysis. This paper has demonstrated how to use SRAM decoder scheme knowledge, detailed layout tracing and Photon Emission Microscope (PEM) analysis to deal with the challenges and find the root causes for several cases of SRAM logic type failures.

This content is only available as a PDF.
You do not currently have access to this content.