Focused ion beam (FIB) circuit edit (CE) is an integral part of IC debug, fault-isolation, and low yield analysis. Regarding FIB microsurgery, complexity is growing with the shrinking of dimensions of lower level metallization while the redistribution layer (RDL) structures can increase in all three dimensions. This requires continuous development of CE processes to address these opposite dimension trends and material variations. There are two venues to address CE, accessing from the front side (FS) or from the back side (BS) of an IC. This paper describes the FS techniques and methodologies developed to edit the RDL technology. The goal of this work is to demonstrate on a Cu GND/power plane the performance of the halogen-based contamination process. Results shows that the benefit of reduced time to remove thick Cu metallization is surely advantageous for CE throughput as well as for improving edit success rates.