In this paper, a zero yield case relating to a systematic defect in N+ poly/N-well varactor (voltage controlled capacitor) on the RF analog circuitry will be studied. The systematic problem solving process based on the application of a variety of FA techniques such as TIVA, AFP current Imaging and nano-probing, manual layout path tracing, FIB circuit edit, selective etching together with Fab investigation is used to understand the root cause as well as failure mechanism proposed. This process is particularly critical for a foundry company with restricted access to data on test condition setup to duplicate the exact failure as well as no layout tracing available at time of analysis. The systematic defect was due to gate oxide breakdown as a result of implanter charging. It serves as a good reference to other wafer Fabs encountering such an issue.