Abstract

Analog simulation combined with Time Resolved Light Emission (TRE) can be used to evaluate different fault possibilities and to isolate the most likely fault candidate. In this paper we will describe an improved fault model derived from parasitic layout extraction.

analog simulation, failure analysis, fault modeling, parasitic layout extraction, time resolved light emission
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Copyright © 2012 ASM International. All rights reserved.
2012
ASM International
Topics
Semiconductor wafer fabrication Process modeling and simulation
Issue Section:
Software Tools for Failure Analysis
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