DRAM Cell Fault Localization Using Passive Voltage Contrast

This paper presents the memory cell level passive voltage contrast (PVC) involving diode, capacitor and transistor devices in a (dynamic random access) DRAM chip. More particularly, we show that the voltage contrast sensitivity can be improved significantly by the adjustment of scan location and scan location sequence. Both leaky and resistive fault localizations by PVC imaging are presented to illustrate our point.