It was already demonstrated, that the method of Lock-in Thermography (LIT) enables 3D localization of thermal active defects, e.g. electrical shorts and resistive opens, on die level and within fully packaged single and multichip devices [1,2]. The depth of a defect can be derived from phase shift measurements of the defective compared to a reference device For a general approach of this method, thermal modeling is used and verified by experimental data to investigate the internal heat propagation under periodic stimulation in correlation to the LIT measuring process. [3]. A basic requirement for the successful application of the method is a precise and reproducible measurement of both the thermal material properties of each material layer and the phase shift between the internal heat excitation and thermal response measured by LIT. Significant influences from the material and measurement setup to the detected phase shift have to be identified and taken into account. However, to identify and distinguish the relevant influences measurements with defined internal heat sources are necessary which are presented in this paper. First, the relationship between geometrical thickness of a material layer and the resulting thermal parameters for both homogeneous and heterogeneous materials are measured and discussed. A new measurement setup generating a defined point heat source will be presented to calibrate the LIT system for quantitative phase shift measurements and to determine the phase shift to thickness parameters of single material layers. In addition the variation of the phase shift caused by the defect geometry and the defect environment will be investigated. Finally, a case study is presented comparing the experimental results to the obtained results from a real stacked die device.

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