Abstract
Circuit Edit and Optical Probe technologies must scale with Intel’s 2 year process cycle and the tick-tock design model. Geometry shrinking combined with revolutionary and evolutionary process changes such-as high-k and metal gate, lower-k interlayer dielectrics, and non-planar devices, make this very challenging. To develop new tools, analytical processes, and validate if the current tool suite can analyze next generation process node and architectures, a special debug block has been designed into Intel’s process test vehicle. In this paper the authors first provide an overview of the Debug Block, we then provide an overview of the LADA, IREM, LVP, TRE, and FIB tools and their corresponding technical challenges for Intel’s next generation microprocessors. Finally we discuss the circuits, layout, and 32nm results.
