In this work, crystalline defects (dislocations) occurred in the silicon substrate during annealing SOD (Spin On Dielectric) which is an easy choice for its superior STI gap-fill ability. The reversal of address data that share same SIO (Signal Input Out) line in a DQ arises from crystalline defects. The failure analysis of physical methods has difficulty finding minute defects within the active because it is scarcely detectable from the top view. Situation can be well understood by electrical analysis using the nano probe. Due to its ability to probing contact nodes around the fail area, a ring type crystalline defect which is hardly detected from the top view was effectively analyzed by 3D TEM with the assistance of nano probe. This work shows that hybrid analysis of electrical method by nano probe and physical method by 3D TEM is useful and effective in failure analysis in semiconductor.