Owing to the limitations of physical failure analysis (FA) techniques and fault localization techniques, the nano-probing tool, which has both the device characterization ability as well as the necessary sensitivity to characterize the non-visible defects and marginal fails, has emerged to be a powerful tool in the FA community. This paper presents a nano-probing technique on two yield impact cases in dynamic random access memory technology. The first case is related to a die that exhibited a high pin current issue during the parametric test sequence at the early stage of our probe test. The second case is related to a column fail expanding across a shared sense amplifier (SA) circuit. By comparing the nano-probing electrical results with simulation data and wafer acceptance test data, insufficient (S/D) contact implant which causes slower p-MOS turn-on and resistive source contact that causes lower driving ability in a SA transistor issue are concluded.