This paper presents a novel backside de-processing technique for effective failure analysis of advanced multi-level interconnect metallization CMOS ICs with flip chip package.

40 nm process, backside de-processing, CMOS integrated circuits, failure analysis, flip chip package, multi-level interconnect metallization
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Copyright © 2011 ASM International. All rights reserved.
2011
ASM International
Topics
Specimen preparation Semiconductor wafer fabrication
Issue Section:
Sample Preparation
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