Abstract

High performance source/drain (S/D) stress-memorization technology (SMT) has been previously demonstrated to enhance electron mobility in leading edge SRAM NMOS designs. Dislocations initiating from SMT induced stacking faults cause electrical fails in the device. Transmission electron microscopy (TEM) results show that these dislocations can be reduced by controlling certain processing steps following SMT processing.

dislocations, electron mobility, stacking faults, stress-memorization-technology, transmission electron microscopy
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Copyright © 2011 ASM International. All rights reserved.
2011
ASM International
Topics
Stacking faults Transmission electron microscopy Semiconductor wafer fabrication
Issue Section:
Nanoprobing
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