There are two known failure mechanisms that cause Gate Disturb failures in flash devices. One main electrically classified failure is the Gate Disturb failure. A second mechanism is the Floating Gate charging caused by high energetic electrons, so-called channel hot electrons, jumping above the energetic barrier of tunnel oxide. This paper describes the characterization of a single transistor Flash cell with the nano-probing approach and introduces a test algorithm to distinguish between these mechanisms at a Gate Disturb affected Flash cell. A Keithley parameter analyzer in combination with Atomic Force Probing (AFP) has been used for the Flash cell device characterization. A Gate Disturb defect can be induced by different defect mechanisms. Two of them, TRAP's in tunnel oxide and channel hot electrons as a result of leaky PN-junctions, were identified as the main root causes. These mechanisms can be distinguished by AFP-analysis with the tests presented in the paper.

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