Contrary to traditional packages, packaging and testing of wafer-level chip scale package (WLCSP) are done before wafer dicing. The package can’t be rebuilt on a single chip; therefore, the failure analysis and debug performed by Circuit Edit (CE) on ICs with WLCSP face challenges. In addition, there are route designs on the package level of WLCSP devices, which are unique compared with traditional packages. CE is required on both chip and package level of WLCSP devices. This package technology offers the smallest possible package size; consequently, it has seen wider use lately. Developing the approaches of FIB edits on a fully-packaged WLCSP device is indeed essential. Thus, methodologies for CE and debug on WLCSP devices will be explored in this study.