The finite, non-zero resistance of the metal wires that define the power grid of chips require the insertion of multiple ports between the grid and the external power supply in order to meet voltage stability requirements across the 2-D plane of the chip. The ports connect to the power grid along its edges for peripheral pad configurations, while, for C4 or array pad configurations, the ports are distributed across the 2-D surface of the chip. In either case, the availability of multiple power ports can be leveraged for detecting and localizing defects and/or Trojan circuits. A localization technique is investigated in this paper that analyzes anomalies introduced by defects and/or Trojans in the measured IDDQs from these ports. The localization accuracy of the technique can be improved significantly through the use of calibration and additional information collected from simulation experiments. The method and model are validated using data collected from a set of chips fabricated in an IBM 65 nm SOI process.1

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