Normally, ESD-type of damage will be located near the bonding pads for the input pins. However, there have been several cases where ESD-type damage has been detected on CMOS gates at internal locations on the die, two or more transistors away from any input or output pin. This paper describes two examples of this type of failure and the unique approaches to the analysis and the special procedures needed to locate the damage sites. It shows some possible approaches to apply to device failures, which do not follow the typical pattern. One of the approaches is a sequence of steps ranging from benign to destructive as shown. The special conditions are usually: the device has functionally failed; curve tracing of the external pins shows no abnormalities; optical and/or SEM inspection of the die will not show any damage sites; and liquid crystal or other thermal techniques will not be effective.

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