One issue that faces failure analysis at the system level is impedance mismatched transmission lines resulting from developers pushing the edge of trace layout recommendations. When transmission lines on printed circuit boards are routed in such a way as to allow for impedance mismatches, the effects can be unwanted on the signal that the line carries. Techniques can be used for discovering if capacitance, resistance, or split planes are creating the impedance mismatches that are resulting in the system level failure seen by the customer.

capacitance, electrical resistance, failure analysis, printed circuit boards, transmission line faults
This content is only available as a PDF.
Copyright © 2010 ASM International. All rights reserved.
2010
ASM International
Topics
Semiconductor wafer fabrication Capacitance Electrical resistance
Issue Section:
System Level Analysis
You do not currently have access to this content.