Flash memory is one of the most mysterious and difficult structures in the semiconductor industry. Excessive data gain and data loss may cause errors in reading the flash memory. This paper discusses the data gain mechanism and the various failure mechanisms (i.e., CoSi at Mux, CoSi at bit, particle at Mux, resistive contact, erasing defect at failing bit, programming fail at bit, misaligned contact, passive voltage contrast (PVC) at multiple gates in Mux region, particle and missing via, poly residue defect etc.) causing single bit flash data gain. Presented in the paper are the definitions involved, Flash cell theory and physics involved, and the theory explaining why leakage in the 8:1 mux causes the single bit flash data gain. This is followed by a case study involving various failure mechanisms and a final conclusion. Knowing the fail mechanisms and correcting them promptly enhances the yield.

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