Abstract

In an effort to understand the failing mechanism of power to ground (Vdd-GND) shorts found on FPGA devices by standard ATE methods at Final Test; the recently discovered ESDFOS (Electro Static Discharge from Outside to Surface)[1] mechanism was revealed as the perpetrator. This ESDFOS was first brought to the attention of the authors when it was seen in the May 2005 issue of the EDFA magazine [2].The physical signatures of ESDFOS such as cracked SiN passivation, Al metal filament spiking, SiO2 dielectric break down can often be related to other failing mechanisms and it can therefore be difficult to irrefutably associate those physical signature to ESDFOS and to make a strong case for action. In this paper standard front side FIB cross sections combined with a novel backside technique were used to establish that the failing devices underwent an ESDFOS event prior to the epoxy encapsulation process. Using the failure analysis results alterations were made to the assembly process which have reduced the occurrence of Vdd-GND shorts.

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